ASICs and FPGAs are used to implement large systems that include million of gates and megabits of embedded memory. The complexity of large systems often requires the use of EDA tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) flow are synthesis, technology mapping, clustering, placement, and routing.
In the past, physical synthesis was optionally used to perform a series of circuit transformations to optimize the design of the system. Unlike traditional synthesis, physical synthesis may take into account the technology and architecture of the target device and delays associated with signals on the target device while performing the circuit transformations to optimize the design of the system. Physical synthesis would typically be performed at a single point after placement and before routing to improve the delays on connections to be routed. Estimates of interconnect delay obtained from existing placement could be used to guide physical synthesis transformations that restructure the circuit on or near a critical path.
Traditional physical synthesis techniques performed after placement and before routing, however, were not as effective in optimizing other goals in the design of systems. Thus, what is needed is an efficient method and apparatus for applying physical synthesis to other goals in the design of a system on an ASIC or FPGA.